Computing systems use a relatively large amount of low-cost main memory as the next level of a memory hierarchy after smaller, faster and more expensive cache memories. The main memory is typically dynamic random-access memory (DRAM) that stores each bit of data in a separate capacitor within an integrated circuit. Although the DRAM uses a different storage technology than the static random access memory (SRAM) used for the cache memories, each of the SRAM and the DRAM includes volatile memory. Volatile memory maintains data for as long as power is applied. In order to support systems where the power can be removed for extended periods of time, or where the constant power requirement for DRAM conflicts with low-power mechanisms in the system, a combination of RAM and read only memory (ROM) is used.
In contrast to using a combination of RAM and ROM, non-volatile memory (NVM) is sometimes used. Non-volatile memory technologies include resistive random access memory (ReRAM) and phase-change random access memory (PRAM), and provide byte addressable access to non-volatile memory. The non-volatile memory provides better scalability and lower cost compared to DRAM at much lower idle power. System developers are able to attach the non-volatile memory directly to the processor memory bus and allow applications to directly access the non-volatile memory through load and store instructions (read and write operations). However, as the density of the non-volatile memory increases, the latencies for the read and write operations increase significantly. The increase in latency for the non-volatile memory results in cache misses, which in turn adds a significant number of clock cycles to the completion of load instructions. In some cases, the cache accesses take thousands of clock cycles to retrieve the desired data from the non-volatile memory. In such cases, system performance degrades below the performance of comparable systems using only DRAM as main memory.
In view of the above, efficient methods and systems for reducing latencies of main memory data accesses are desired.
While the invention is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the scope of the present invention as defined by the appended claims.